`include "files/alucode_defines.v"
module mem(
	input				clk,rst,
	input 	[31:0]		mem_JumpAddr,
	input	[31:0]		mem_Addr,
	input	[7:0]		mem_Code,
	input	[31:0]		mem_ALURes,
	input	[31:0]		mem_WrData,
	input 	[31:0]		mem_RFWAddr,

	output	[31:0]		wb_Addr,
	output 	[31:0]		wb_Code,
	output	[31:0]		wb_OData,
	output	[31:0]		wb_RFWAddr,
	output  [31:0]       wb_Pin
);

reg 	[31:0]		reg_JumpAddr;
reg 	[31:0]		reg_Addr;
reg 	[7:0]		reg_Code;
reg 	[31:0]		reg_ALURes;
reg 	[31:0]		reg_WrData;
reg 	[31:0]		reg_RFWAddr;
// reg     [3:0]       reg_pin;
// assign wb_RFWAddr = reg_RFWAddr;
// assign wb_Addr = reg_Addr;
assign wb_Code = reg_Code;
// assign wb_OData = reg_OData;
assign wb_RFWAddr = reg_RFWAddr;

always @(posedge clk or negedge rst) begin
	if (!rst) begin
		// reset
		
	end
	else begin
		reg_JumpAddr <= mem_JumpAddr;
		reg_Addr <= mem_Addr;
		reg_Code <= mem_Code;
		reg_ALURes <= mem_ALURes;
		reg_WrData <= mem_WrData;
		reg_RFWAddr <= mem_RFWAddr;
	end
end

wire [31:0] addr;
assign wb_Addr = addr;
MUX inst_MUX (
	.sinal    (reg_Code[5]),
	// .in_data0 (reg_Addr),
	.in_data0 (0),
	.in_data1 (reg_JumpAddr),
	.out_data (addr)
);

wire [31:0]	rdata;
DataMem inst_DataMem (
	.address (mem_ALURes),
	// .clken   (clken),
	.clock   (clk),
	.data    (mem_WrData),
	.wren    (mem_Code[0]),
	.q       (rdata)
);
pin inst_pin (
	.wsignl(reg_Code[0]), 
	.addr(reg_ALURes), 
	.wdata(reg_WrData), 
	.o(wb_Pin)
);



MUX3MEM inst_MUX3MEM (
	.sinal    (reg_Code[3:2]),
	.in_data1 (reg_ALURes),
	.in_data2 (rdata),
	.in_data3 (addr),
	.out_data (wb_OData)
);



endmodule